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GAL26CV12
High Performance E2CMOS PLD Generic Array LogicTM Features
* HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- 7.5 ns Maximum Propagation Delay -- Fmax = 142.8 MHz -- 4.5ns Maximum from Clock Input to Data Output -- TTL Compatible 16 mA Outputs -- UltraMOS(R) Advanced CMOS Technology * ACTIVE PULL-UPS ON ALL PINS * LOW POWER CMOS -- 90 mA Typical Icc * E2 CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * TWELVE OUTPUT LOGIC MACROCELLS -- Uses Standard 22V10 Macrocells -- Maximum Flexibility for Complex Logic Designs * PRELOAD AND POWER-ON RESET OF REGISTERS -- 100% Functional Testability * APPLICATIONS INCLUDE: -- DMA Control -- State Machine Control -- High Speed Graphics Processing -- Standard Logic Speed Upgrade * ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
I/CLK
RESET
INPUT 8
I 8 I 8 I 8 I
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
PROGRAMMABLE AND-ARRAY (122X52)
OLMC
I/O/Q
10
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I 8 I 8 I 8 I 8 I
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
PRESET
I/O/Q
Description
The GAL26CV12, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance 28-pin PLD available on the market. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. Expanding upon the industry standard 22V10 architecture, the GAL26CV12 eliminates the learning curve typically associated with using a new device architecture. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL26CV12 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 devices. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Pin Configuration
DIP PLCC
I/CLK I/O/Q I/O/Q
I/CLK I I I I
1
28
I I/O/Q I/O/Q
4
2
28
26 25
I I VCC I I I I
5
I/O/Q I/O/Q I/O/Q I/O/Q GND I/O/Q I/O/Q
I Vcc I I I I I I I 7
GAL 26CV12
21
I
I/O/Q I/O/Q I/O/Q I/O/Q GND I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q
I
I
7
I
GAL26CV12
Top View
12 14 16
23
9
21
11
19 18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
14
15
I/O/Q
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
26cv12_03
1
Specifications GAL26CV12
GAL26CV12 Ordering Information
Commercial Grade Specifications
Tpd (ns)
7.5
Tsu (ns)
6
Tco (ns)
4.5
Icc (mA)
130 130
Ordering #
GAL26CV12C-7LP GAL26CV12C-7LJ GAL26CV12B-10LP GAL26CV12B-10LJ GAL26CV12B-15LP GAL26CV12B-15LJ GAL26CV12B-20LP GAL26CV12B-20LJ
Package
28-Pin Plastic DIP 28-Lead PLCC 28-Pin Plastic DIP 28-Lead PLCC 28-Pin Plastic DIP 28-Lead PLCC 28-Pin Plastic DIP 28-Lead PLCC
10
7
7
130 130
15
10
8
130 130
20
12
12
130 130
Industrial Grade Specifications
Tpd (ns)
10
Tsu (ns)
7
Tco (ns)
7
Icc (mA)
150 150
Ordering #
GAL26CV12C-10LPI GAL26CV12C-10LJI GAL26CV12B-15LPI GAL26CV12B-15LJI GAL26CV12B-20LPI GAL26CV12B-20LJI
Package
28-Pin Plastic DIP 28-Lead PLCC 28-Pin Plastic DIP 28-Lead PLCC 28-Pin Plastic DIP 28-Lead PLCC
15
10
8
150 150
20
12
12
150 150
Part Number Description
XXXXXXXX _ XX X XX
GAL26CV12C Device Name GAL26CV12B Speed (ns) L = Low Power Power Grade Blank = Commercial I = Industrial
Package P = Plastic DIP J = PLCC
2
Specifications GAL26CV12
Output Logic Macrocell (OLMC)
The GAL26CV12 has a variable number of product terms per OLMC. Of the twelve available OLMCs, two OLMCs have access to twelve product terms (pins 20 and 22), two have access to ten product terms (pins 19 and 23), and the other eight OLMCs have eight product terms each. In addition to the product terms available for logic, each OLMC has an additional product term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The GAL26CV12 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen.
AR
D Q CLK SP Q
4 TO 1 MUX
2 TO 1 MUX
GAL26CV12 OUTPUT LOGIC MACROCELL (OLMC)
Output Logic Macrocell Configurations
Each of the Macrocells of the GAL26CV12 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the the following page. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC's D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop's /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product term for each output, and may be individually set by the compiler as either "on" (dedicated output), "off" (dedicated input), or "product term driven" (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array.
3
Specifications GAL26CV12
Registered Mode
AR
AR
D
Q
D
Q
CLK SP
Q
CLK SP
Q
ACTIVE LOW S0 = 0 S1 = 0 S0 = 1 S1 = 0
ACTIVE HIGH
Combinatorial Mode
ACTIVE LOW S0 = 0 S1 = 1 S0 = 1 S1 = 1
ACTIVE HIGH
4
Specifications GAL26CV12
GAL26CV12 Logic Diagram/JEDEC Fuse Map
DIP & PLCC Package Pinouts
1
0 4 8 12 16 20 24 28 32 36 40 44 48
0000 0052 . . . 0468
ASYNCHRONOUS RESET (TO ALL REGISTERS)
28
8
OLMC
S0 6344 S1 6345
27
2
0520 . . . 0936
8
OLMC
S0 6346 S1 6347
26
3
0988 . . . 1404
8
OLMC
S0 6348 S1 6349
25
4
1456 . . . 1872
8
OLMC
S0 6350 S1 6351
24
5
1924 . . . . 2444
10
OLMC
S0 6352 S1 6353
23
6
2496 . . . . . 3120
12
OLMC
S0 6354 S1 6355
22
8
3172 . . . . . 3796
12
OLMC
S0 6356 S1 6357
20
9
3848 . . . . 4368
10
OLMC
S0 6358 S1 6359
19
10
4420 . . . 4836
8
OLMC
S0 6360 S1 6361
18
11
4888 . . . 5304
8
OLMC
S0 6362 S1 6363
17
12
5356 . . . 5772
8
OLMC
S0 6364 S1 6365
16
13
5824 . . . 6240
8
OLMC
S0 6366 S1 6367
15
14
6292
SYNCHRONOUS PRESET (TO ALL REGISTERS)
6368, 6369 ...
M S B L S B
Electronic Signature
... 6430, 6431
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
5
Specifications GAL26CV12C Specifications GAL26CV12
Absolute Maximum Ratings(1)
Supply voltage VCC ...................................... -0.5 to +7V Input voltage applied .......................... -2.5 to VCC +1.0V Off-state output voltage applied ......... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Ambient Temperature with Power Applied ........................................... -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (TA) ........................... -40 to 85C Supply voltage (VCC) with Respect to Ground ......................... +4.5 to +5.5V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25C 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN.
Vss - 0.5
TYP.3 -- -- -- -- -- -- -- -- --
MAX. 0.8 Vcc+1 -100 10 0.5 -- 16 -3.2 -130
UNITS V V A A V V mA mA mA
VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2
2.0 -- -- -- 2.4 -- -- -30
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open
L-7
--
90
130
mA
INDUSTRIAL ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open
L-10
--
90
150
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 C.
6
Specifications GAL26CV12C Specifications GAL26CV12
AC Switching Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
COM PARAM IND
TEST COND.1 A A -- -- -- -- A
DESCRIPTION MIN. Input or I/O to Comb. Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Fdbk before Clk Setup Time, SP before Clock Hold Time, Input or Fdbk after Clk Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynch. Reset of Reg. Asynchronous Reset Pulse Duration Asynch. Reset to Clk Recovery Time Synch. Preset to Clk Recovery Time 1 1 -- 6 6 0 95.2
-7 MAX. 7.5 4.5 2.5 -- -- -- --
-10 MIN. MAX. 1 1 -- 7 7 0 71.4 10 7 2.5 -- -- -- -- UNITS ns ns ns ns ns ns MHz
tpd tco tcf2 tsu1 tsu2 th
fmax3
A A
117.6 142.8
-- --
105 105
-- --
MHz MHz
twh twl ten tdis tar tarw tarr tspr
-- -- B C A -- -- --
3.5 3.5 1 1 1 7 5 5
-- -- 7.5 7.5 9 -- -- --
4 4 1 1 1 8 8 10
-- -- 10 9 13 -- -- --
ns ns ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section.
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 8 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
7
Specifications GAL26CV12B Specifications GAL26CV12
Absolute Maximum Ratings(1)
Supply voltage VCC ...................................... -0.5 to +7V Input voltage applied .......................... -2.5 to VCC +1.0V Off-state output voltage applied ......... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Ambient Temperature with Power Applied ........................................... -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (TA) ........................... -40 to 85C Supply voltage (VCC) with Respect to Ground ......................... +4.5 to +5.5V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25C 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN.
Vss - 0.5
TYP.3 -- -- -- -- -- -- -- -- --
MAX. 0.8 Vcc+1 -100 10 0.5 -- 16 -3.2 -130
UNITS V V A A V V mA mA mA
VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2
2.0 -- -- -- 2.4 -- -- -30
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open
L-10/-15/-20
--
90
130
mA
INDUSTRIAL ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open
L-15/-20
--
90
150
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 C.
8
Specifications GAL26CV12B Specifications GAL26CV12
AC Switching Characteristics
Over Recommended Operating Conditions
COM PARAMETER COM / IND COM / IND
TEST COND.1 A A -- -- -- -- A
DESCRIPTION Input or I/O to Combinatorial Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Feedback before Clock Setup Time, SP before Clock Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynchronous Reset of Register Asynchronous Reset Pulse Duration Asynchronous Reset to Clock Recovery Time Synchronous Preset to Clock Recovery Time 3 2 -- 7 10 0 71.4
-10 MIN. MAX. 10 7 2.5 -- -- -- --
-15 MIN. MAX. 3 2 -- 10 10 0 55.5 15 8 2.5 -- -- -- --
-20 MIN. MAX. 3 2 -- 12 12 0 41.6 20 12 10 -- -- -- -- UNITS ns ns ns ns ns ns MHz
tpd tco tcf2 tsu1 tsu2 th
fmax3
A A
105 105
-- --
80 83.3
-- --
45.4 62.5
-- --
MHz MHz
twh twl ten tdis tar tarw tarr tspr
-- -- B C A -- -- --
4 4 3 3 3 8 8 10
-- -- 10 10 13 -- -- --
6 6 3 3 3 10 10 10
-- -- 15 15 20 -- -- --
8 8 3 3 3 15 15 12
-- -- 20 20 25 -- -- --
ns ns ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section.
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 8 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
9
Specifications GAL26CV12
Switching Waveforms
INPUT or I/O FEEDBACK
VALID INPUT
INPUT or I/O FEEDBACK
VALID INPUT
ts u
th
tpd
COMBINATORIAL OUTPUT
CLK
tc o
Combinatorial Output
REGISTERED OUTPUT
1/
fm a x
(external fdbk)
Registered Output
INPUT or I/O FEEDBACK
tdis
OUTPUT
ten
CLK
1/
fmax (internal fdbk)
Input or I/O to Output Enable/Disable
REGISTERED FEEDBACK
tcf
tsu
fmax with Feedback
tw h
CLK
1/
tw l
fm a x
(w/o fdbk)
Clock Width
INPUT or I/O FEEDBACK DRIVING SP CLK
INPUT or I/O FEEDB ACK DRIVI NG AR
tsu
th
tspr
CLK
tarw
tco
REGISTERED OUTPUT
tarr
R E G I S T ER E D OUTPUT
tar
Synchronous Preset Asynchronous Reset
10
Specifications GAL26CV12
fmax Definitions
CL K
CLK
LOGIC ARR AY
R EG I S T E R
LOGIC ARRAY
REGISTER
ts u
tc o
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
CLK
tcf tpd
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
LOGIC ARRAY
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Times C-7/-10/-15 B-10/-15/-20 GND to 3.0V 1.5ns 10% - 90% 3ns 10% - 90% 1.5V 1.5V See Figure
FROM OUTPUT (O/Q) UNDER TEST TEST POINT R1 +5V
Input Timing Reference Levels Output Timing Reference Levels Output Load
3-state levels are measured 0.5V from steady-state active level. GAL26CV12 Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low R1 300 300 300 R2 390 390 390 390 390 CL 50pF 50pF 50pF 5pF 5pF
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
11
Specifications GAL26CV12
Electronic Signature
An electronic signature is provided in every GAL26CV12 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell.
Output Register Preload
When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in normal machine operation. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL26CV12 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically.
Security Cell
A security cell is provided in every GAL26CV12 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
Latch-Up Protection
GAL26CV12 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential for latch-up caused by negative input undershoots. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots.
Input Buffers
GAL26CV12 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL logic. The input and I/O pins also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. Typical Input Current
I n p u t C u r r e n t (u A )
0
Device Programming
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
-20
-40 -60 0 1.0 2.0 3.0 4.0 5.0
In p u t V o lt ag e ( V o lt s)
12
Specifications GAL26CV12
Power-Up Reset
Vcc Vcc (min.)
tsu
CLK
twl tpr
INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
ACTIVE LOW OUTPUT REGISTER
Device Pin Reset to Logic "1"
ACTIVE HIGH OUTPUT REGISTER
Device Pin Reset to Logic "0"
Circuitry within the GAL26CV12 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some conditions must be met to
provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematics
PIN
Feedback PIN
Vcc
(Vref Typical = 3.2V)
Active Pull-up Circuit
Active Pull-up Circuit
(Vref Typical = 3.2V)
Vcc
ESD Protection Circuit
Vref
Vcc
Tri-State Control
Vcc
Vref
PIN
Data Output
PIN
ESD Protection Circuit
Feedback (To Input Buffer)
Typical Input
Typical Output
13
Specifications GAL26CV12
GAL26CV12C: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
Normalized Tco
1.1
Normalized Tsu
1.1
1.1
1
1
1
0.9
0.9
0.9
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
Normalized Tpd
Normalized Tco
Normalized Tsu
-55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7
1.3 1.2 1.1 1 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0 0
Delta Tco vs # of Outputs Switching
Delta Tpd (ns)
-0.25
Delta Tco (ns)
1 2 3 4 5 6 7 8 9 10 11 12
-0.25
-0.5
-0.5
-0.75
-0.75
-1
-1 1 2 3 4 5 6 7 8 9 10 11 12
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
12 10 12
Delta Tco vs Output Loading
RISE
Delta Tpd (ns)
10
RISE FALL
8 6 4 2 0 -2 0 50
Delta Tco (ns)
150 200 250 300
FALL
8 6 4 2 0 -2
100
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
14
Specifications GAL26CV12
GAL26CV12C: Typical AC and DC Characteristic Diagrams
Vol vs Iol
3 2.5 5 4
Voh vs Ioh
4
Voh vs Ioh
3.75
Voh (V)
3 2 1 0
1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00
Voh (V)
10.00 20.00 30.00 40.00 50.00 60.00
Vol (V)
2
3.5
3.25
3 0.00 1.00 2.00 3.00 4.00
0.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.3 1.3
Normalized Icc vs Temp
1.50
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
Normalized Icc
-55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7 4.50 4.75 5.00 5.25 5.50
1.2 1.1 1 0.9 0.8 0.7
1.40 1.30 1.20 1.10 1.00 0.90 0.80 0 25 50 75 100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
10 0 10
Input Clamp (Vik)
Delta Icc (mA)
8 6 4 2 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Iik (mA)
20 30 40 50 60 -2.00 -1.50 -1.00 -0.50 0.00
Vin (V)
Vik (V)
15
Specifications GAL26CV12
GAL26CV12B: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
1.1
Normalized Tco
Normalized Tsu
1.1
1.1
1
1
1
0.9
0.9
0.9
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
Normalized Tpd
Normalized Tco
Normalized Tsu
-55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7
1.3 1.2 1.1 1 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
Temperature (deg. C)
Delta Tco vs # of Outputs Switching
0
0
Delta Tpd (ns)
-0.5
Delta Tco (ns)
1 2 3 4 5 6 7 8 9 10 11 12
-0.5
-1
-1
-1.5
-1.5
-2
-2 1 2 3 4 5 6 7 8 9 10 11 12
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
12 10 12
Delta Tco vs Output Loading
RISE
10
Delta Tpd (ns)
RISE FALL
8 6 4 2 0 -2 0 50
Delta Tco (ns)
150 200 250 300
FALL
8 6 4 2 0 -2
100
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
16
Specifications GAL26CV12
GAL26CV12B: Typical AC and DC Characteristic Diagrams
Vol vs Iol
3 2.5 5 4
Voh vs Ioh
4.5
Voh vs Ioh
4.25
Voh (V)
3 2 1 0
1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00
Voh (V)
10.00 20.00 30.00 40.00 50.00 60.00
Vol (V)
2
4
3.75
3.5 0.00 1.00 2.00 3.00 4.00
0.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.2 1.3
Normalized Icc vs Temp
1.20
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.1
Normalized Icc
-55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7
1.10
1
1.00
0.9
0.90
0.8 4.50 4.75 5.00 5.25 5.50
0.80 0 25 50 75 100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
10 0 10 20 30 6 4 2 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Delta Icc (mA)
8
Iik (mA)
40 50 60 70 80 90 100 -2.00 -1.50 -1.00 -0.50 0.00
Vin (V)
Vik (V)
17

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